When a computer system is designed or set up, verification of various types of operations is performed. For example, in a computer system having a central processing unit (CPU) or a processor, an input/output (I/O) device and a memory, a method in which a test program is executed by the CPU to generate memory access has been utilized for performing verification of a dual inline memory module (DIMM) and a memory access control section.
Furthermore, a test circuit is also known which performs memory access in order to access a specified address without execution of an instruction using a CPU, thereby verifying an operation.
Similarly, a test circuit is known that performs verification of an operation of an interface that is operating as a single device for verifying an external interface. As one example, a test circuit is known in which an output terminal of an interface is connected to an input terminal thereof to form a return path for testing a serial interface circuit. In such circuit, a test pattern is generated by a test pattern generating unit at the output terminal when the test is performed, and an operation check is performed by a matching circuit for matching of the test pattern at the input terminal.
These test circuits performs verification of a memory or a circuit without setting up a system after all peripheral devices are connected to the system in a practical manner, and without running a test program on the system.
Technologies related to tests are disclosed in the following documents: Japanese Unexamined Patent Application Publication No. 2005-182263; Japanese Unexamined Patent Application Publication No. 5-342111; and Japanese Unexamined Patent Application Publication No. 2001-67274.
In order to satisfy demand for higher performance in recent years, the configuration of systems has become complicated. Accordingly, reduction of a time taken to perform system verification is required to reduce a development time. In order to realize setting up of such a system which is complicated and whose development time is short, it is required to perform various types of verification on the system at a step before other peripheral devices are connected to the system.
However, in a case in which various types of operation tests are performed using the above-mentioned test circuits on the system at a step before other peripheral devices are connected to the system, as the number of memory addresses to be tested or the number of test patterns is increased, the configuration and circuit scale of the system are increased. Accordingly, there is a problem that a fundamental advantage that testing can be easily performed is lost.
Realization of a technology for performing, with a simple mechanism, various types of verification on system elements that exist in a wider area is an important issue. More particularly, in a server device in which a plurality of CPUs is mounted, the configuration of a system is complicated, and it takes a long time to perform verification when the system is set up. Accordingly, how to easily perform various types of tests at a step before the CPUs are connected to the system is important.
Embodiments of the present invention are made to solve the above-described issues.